The difficulty of reading data from memory sectors in which the data is stored, while erasing or programming other memory sectors, has always limited the performance of non-volatile FLASH memory devices. Erase operations that may be carried out per sector may last about 1 second, and the time required for programming or writing data in a certain memory sector is about the same or even longer.
During these intervals it is difficult to run a program code or read data even if the data is stored in a different sector from the ones involved in the erasing and/or programming operation. The problem is even more accentuated in the case of multi-level non-volatile memory devices, that is, memory devices in which more than one bit per cell may be stored. In these memory devices, the charge stored in the floating gate is fractioned and generates 2nb distributions, where “nb” is the number of bits that may be stored in a single cell. The improved precision that is required is not limited only to the read operation but also to the programming process, and must ensure a correct positioning of an electrical charge in the cells according to the different distributions. This implies an increased duration of the verification and program routines.
To overcome such a severe limitation, an architecture that allows data to be accessed and read from different sectors while an erasing operation is being carried out in other sectors is disclosed in U.S. Pat. No. 5,748,528. The architecture described in this patent, besides requiring a non-negligible silicon area, still has some limits with respect to reading data from the memory while data is being erased or programmed in other sectors.
FIG. 1 illustrates the basic aspect of this known architecture. Not withstanding an advantageous order of row address lines or wordlines, called main wordlines (MWL), and an advantageous order of column address lines or bitlines, called main bitlines (MBL), the connection between a main wordline and the relative local wordlines as well as the connection among a main bitline and the relative local bitlines is realized through local row decoders LOCAL ROW DECODER and local column decoders LOCAL COLUMN DECODER. These local decoders implement a multiplexing function, for example a 4-to-1 multiplexing. In practice, four local bitlines correspond to a main bitline and two address bits are used to select which bitline of the four local bitlines must be connected to the corresponding main bitline.
Data is written in the cells of a certain sector SECTOR in the same way as normally done in a non-volatile, NOR type FLASH_EEPROM memory, that is, using channel hot electrons (CHE). The writing of data is carried out by applying a potential of about 10V on the control gate, a voltage of about 5V on the drain and leaving the source connected to ground. In these conditions an intense electric field between the isolated gate and the channel is generated, together with a relatively large current between the source and drain. This allows the electrons, which acquires a high kinetic energy on their travel from the source to the drain, to jump from the channel to the floating gate by overcoming the potential barrier formed by the tunnel oxide. This type of process is self-limiting. In fact, the negative charges accumulated in the floating gate reduce the initially generated electric field, thus contrasting progressively the cause of the charge accumulation.
The selected memory cell is biased to the programming conditions by selecting the relative main wordline and the relative local wordline that are biased at a positive programming voltage, and the main bitline and the local bitline that are biased at the programming drain voltage. This situation makes it difficult to bias to a reading condition other cells accessible through the same main wordline or through the same main bitline, even if they belong to a different sector of the matrix of memory cells.
There is the need of an architecture for a flash EEPROM non-volatile memory device that overcomes this inability of reading memory cells that, even if belonging to a different sector from that involved in the erasing and/or writing operations, are accessed through the same main wordlines and bitlines of the cells that are being erased and/or written, without excessively increasing the silicon area of the memory device.